PROGRAM

SESSION F

Radiation Hardening Techniques

Chairs: Florence Malou & Fernanda Kastensmidt

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F-1

Influence of Device Geometry and Buffer Design on the SEE Response of GaN-on-Si Power Transistors

Authors: A. Moreno(1), M. Basler(2), D. Fugmann(2), D. Koch(3), A. Reck(3), M. Pradhan(4)
1. TESAT / Airbus DS, Germany,
2. Fraunhofer Institute for Applied Solid State Physics (IAF), Germany,
3. University of Stuttgart, Germany,
4. IMS CHIPS, Germany

Presenting author: Alberto Moreno

Heavy-ion testing of GaN-on-Si power HEMTs with systematic geometry variations identifies two hardening levers: field plates cause IDSS SELC without affecting the SEB threshold -decoupling the two- and the AlN/GaN superlattice buffer drives part-to-part variability.

F-2

Demonstration of the First 400 V Radiation-Hardened β-Ga2O3 Power Transistor Featuring RESURF Structure

Authors: D. Yu(1), S. He(1), H. Wu(1), X. Zhou(1), X. Xie(1), J. Wen(1), T. Wang(2), L. Shu(3), G. Xu(1), S. Yang(1), B. Li(1), S. Long(1)
1. University of Science and Technology of China, China,
2. Harbin Institute of Technology, China,
3. Institute of Microelectronics of the Chinese Academy of Sciences, China

Presenting author: Da Yu

This work presents the first experimental investigation of the single-event effects (SEEs) of β-Ga2O3 transistors and demonstrates a radiation-hardened β-Ga2O3 junction field-effect transistor (RH-JFET) featuring reduced-surface field (RESURF) structure.

F-3

An SET-Tolerant Wideband On-Chip Clock Generator Using ISF-Guided Design Strategy

Authors: H. Sang(1), H. Yuan(1), Y. Chen(2), Y. Guo(2), P. Huang(2), S. Liu(2), Y. Wang(2)
1. National University of Defense Technology, China,
2. National University of Defense technology, China

Presenting author: Hao Sang

An ISF-guided hardening strategy for SET-tolerant LC-VCOs in a wideband clock source is presented. Fabricated in FinFET technology, it achieves 17.6 kHz–3.2 GHz, 1.5 nJ SET threshold, and 0.07% frequency deviation under heavy-ion irradiation.

F-4

A Transformer-Based LC-VCO for Space Applications: Low SET Sensitivity Demonstrated by Two-Photon Absorption Laser Testing

Authors: K. Onishi(1), S. Kano(1), T. Ichikawa(1), N. Usami(2), K. Sakamoto(3), D. Kobayashi(2), T. Iizuka(1)
1. Department of Electrical Engineering and Information Systems, the University of Tokyo, Japan,
2. Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Japan,
3. Research and Development Directorate, Japan Aerospace Exploration Agency, Japan

Presenting author: Keisuke Onishi

A transformer-based LC-VCO is integrated in a 65-nm CMOS PLL, evaluated using two-photon absorption laser testing. Compared with a conventional varactor-based LC-VCO, it exhibits no SET-induced disturbances and improved SET hardness, supporting radiation-hardened frequency synthesis.

F-5

Identification and Layout-Level Mitigation of Single-Event Latchup in NCAP-Based CMOS Structures

Authors: D. Truyen(1), R. Bouakaz(1), L. Montagner(1), B. Treuillard(1)
1. Microchip, France

Presenting author: David Truyen

This work investigates SEL root causes in a complex integrated circuit using layout analysis, heavy-ion, and pulsed-laser testing. A grounded NCAP cell near a PMOS is identified as sensitive, and a TCAD-based mitigation is proposed.

POSTERS

PF-1

Distributed-Voter Triple Modular Redundancy Comparative Study

Authors: D. Gonzalez-montesoro(1), A. Serrano-cases(2), R. Bastos(3), S. Cuenca-asensi(1), E. Atukpor(4), A. Martinez-alvarez(1)
1. University of Alicante, Spain,
2. Alicante University, Spain,
3. Univ. Grenoble Alpes / TIMA laboratory, France,
4. Institut Laue-Langevin, France

Presenting author: Dario Gonzalez-Montesoro

This work evaluates reliability and performance of a Rust-based Distributed Voter for TMR, eliminating the single point of failure through safe multithreading; neutron irradiation shows no worsening fault sensitivity with reliability comparable to C implementations.

PF-2

A Radiation-Hardened Bandgap Reference Circuit for Active Pixel Sensors

Authors: P. Li(1), H. Zhu(1)
1. Zhejiang University, China, China

Presenting author: Pengxu Li

A radiation-hardened bandgap reference in a 180-nm CMOS process employing an adaptive feedback calibration loop is proposed. Irradiated up to 250 Mrad(SiO$_2$), the design maintains reference voltage variation within 2%, confirming the radiation tolerance.

PF-3

Evaluation of error mitigation techniques for RISC-V soft cores under proton irradiation

Authors: J. Cano(1), L. Entrena(2), M. Garcia-valderas(3), A. Lindoso(4)
1. Universidad Carlos III de Madrid, Spain,
2. Universidad Carlos III, Spain,
3. University Carlos III of Madrid, Spain,
4. University Carlos III Madrid, Spain

Presenting author: Jorge Cano

This work evaluates error mitigation for RISC-V soft cores on SRAM-based FPGAs using proton irradiation. It analyzes trade offs between error detection and hardware overhead, and compares vendor supported protections with custom mitigation techniques.

PF-4

Neutron Characterization of a Fault-Tolerant Pipelined RISC-V SoC and Instruction Cache

Authors: W. Grignani(1), D. Santos(1), M. Kastriotou(2), C. Cazzaniga(2), D. Melo(3), F. Wrobel(4), L. Dilillo(1)
1. IES, University of Montpellier, CNRS, France,
2. STFC, United Kingdom,
3. Univali, Brazil,
4. Universite Montpellier, France

Presenting author: Wesley Grignani

This work evaluates a pipelined RISC-V SoC under neutron irradiation. We analyze the performance, resource utilization, and reliability trade-offs of integrated, hardened instruction cache configurations, demonstrating effective fault mitigation strategies for dependable applications.

PF-5

Receiver-State-Aware Adaptive Equalization for X-Ray Irradiated TSV Channels With ADC Radiation Effects

Authors: B. Liang(1)
1. Xidian University, China

Presenting author: Bo Liang

This paper proposes an adaptive equalization method for X-ray irradiated TSV channels with ADC degradation. The method is validated over 0-250 krad(Si), and it improves eye height by 10.9% and eye width by 25.1%.