PROGRAM

SESSION E

Radiation Effects in Complex Devices and Systems

Chairs: Alejandro Urena & Paolo Rech

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E-1

Characterization of the STRV-R2 radiation-hard RISC-V microcontroller in 28nm CMOS for high-energy physics experiments

Authors: M. Karagounis(1), S. Garcia(1), J. Kampkoetter(1), M. Sansare(1), A. Walsemann(2)
1. University of Applied Sciences and Arts Dortmund, Germany,
2. University of Bonn, Germany

Presenting author: Michael Karagounis

A 28 nm radiation-hard RISC-V microcontroller is characterized under TID and SEE. Robust operation without SEFIs is demonstrated, while delay effects, SRAM resilience, TMR effectiveness, and POC-induced reset vulnerability are analyzed.

E-2

Diverse Failure Modes of an STM32 Microcontroller Under Gamma Dose Rate Testing

Authors: I. Garfield(1), J. Farnsworth(2), M. Wirthlin(1), J. Goeders(1)
1. Brigham Young University, USA,
2. Brigham young University, USA

Presenting author: Isaac Garfield

We present gamma dose rate characterization of an STM32L4 microcontroller, identifying diverse failure modes including SRAM upsets, clock perturbations, processor lockup, and novel SRAM power-up preference effects.

E-3

Probing Zephyr RTOS Under Proton Irradiation: Kernel Fault Reporting for Software SEE Analysis

Authors: K. Bresler-przybyl(1), M. Mrozowski(2), K. Sielewicz(3), M. Patecki(2), T. Rajkowski(4)
1. Warsaw University of Technology, Poland,
2. SigmaLabs, Poland,
3. Sigmalabs, Poland,
4. National Centre for Nuclear Research (NCBJ), Poland

Presenting author: Karol Bresler-Przybyl

We present a 51 MeV proton irradiation test of a Zephyr RTOS–based system, showing how kernel error reporting enables system and software‑level Single Event Effects (SEE) analysis on an nRF5340‑based ESA‑PAD Reader Head system.

E-4

Exposing Application-Level Radiation Effects in a RISC-V SoC on a Versal FPGA Through Fault-Aware Design

Authors: T. Lange(1), M. Glorieux(1), M. Khaldouni(2), I. Nofal(1), B. Said(3), C. Poivey(4)
1. IROC Technologies, France, 2. GE Vernova, France, 3. ESA, France, 4. ESA, Netherlands

Presenting author: Thomas Lange

This paper presents the radiation evaluation of a RISC-V SoC on a Versal FPGA using a fault-aware design executing a representative workload for space applications. Heavy-ion irradiation results are compared with fault injection outcomes.

POSTERS

PE-1

Radiation Effects on Vision Transformer Attention Modules in Edge AI Platforms

Authors: L. Frias(1), G. Leon(2), J. Belloch(1), J. Badia(2), A. Lindoso(1)
1. Universidad Carlos III de Madrid, Spain,
2. Universitat Jaume I, Spain

Presenting author: Lester Frias

This study evaluates proton radiation effects on Vision Transformer (ViT) attention modules using an NVIDIA Jetson Orin Nano, characterizing inference reliability by quantifying radiation-induced Silent Data Corruptions and Detected Unrecoverable Errors.

PE-2

ARM vs. RISC-V: A Direct Single-Event Effect Comparison on Shared Silicon

Authors: M. Esterhuyse(1), A. Barnard(1)
1. Stellenbosch University, South Africa

Presenting author: Michael Esterhuyse

This study compares Single-Event Effect (SEE) susceptibility between ARM and RISC-V architectures under heavy-ion irradiation. The RP2350 microcontroller provides shared silicon for both cores, eliminating manufacturing variables to enable direct comparison.

PE-3

A Fault-driven Methodology for Efficient Selective TMR in FINN-Based CNN Accelerators in FPGA RISC-V Systems

Authors: V. Veiga(1), F. Benevenuti(1), N. Medina(2), V. Aguiar(2), S. Alberton(3), A. Beck(1), J. Azambuja(1), F. Kastensmidt(1)
1. Universidade Federal do Rio Grande do Sul, Brazil,
2. Instituto de Física da Universidade de São Paulo, Brazil,
3. University of Sao Paulo, Institute of Physics, Brazil

Presenting author: Vicente Veiga

This work proposes a fault-driven methodology for selective TMR in FINN accelerators. Targeting output-proximal layers achieves 64% of total reliability gains with only 30% area overhead, optimizing fault tolerance for FPGA-based RISC-V AI systems.

PE-4

Mission-Aware Reliability Assessment of SEU Impact on FPGA DPU Accelerators

Authors: F. Buccellato(1), E. Vacca(1), C. Desio(1), S. Azimi(1), L. Sterpone(1)
1. Politecnico di Torino, Italy

Presenting author: Federico Buccellato

This work presents a mission-aware methodology for SEU reliability assessment of FPGA-based DPU accelerators, combining GEANT4 radiation modeling with runtime logits based anomaly detection to quantify inference integrity and support reliability decisions in CubeSats.

PE-5

Single Event Effects characterisation of AMD Versal Programmable Logic

Authors: D. Agiakatsikas(1), V. Vlagkoulis(1), G. Karaoglanian(1), S. Aitzan(1), P. Mihalis(1), S. Bounasser(2), C. Poivey(2)
1. University of Piraeus, Greece,
2. European Space Agency, ESTEC, Netherlands

Presenting author: Dimitris Agiakatsikas

Heavy-ion irradiation experiments are conducted on an AMD Versal device. Results quantify cross-sections of WSR and DSP programmable logic circuits, analyse failure modes, and attribute failures to configuration memory or flip-flop upsets.

PE-6

SET Analysis of FPGA-Based TSN Communication for Space Applications

Authors: M. Duni(1), G. Cora(1), C. De sio(1), S. Azimi(1), L. Sterpone(1)
1. Politecnico di Torino, Italy

Presenting author: Morgana Duni

This paper presents an investigation on the effects and propagation of Single-Event Transients (SET) in Rad-Hard FPGA-based Time-Sensitive Network (TSN) architectures for space-oriented applications.

PE-7

Methodology Development for SEE Laser Testing of a ResNet50 CNN Custom Hardware Accelerator using Versal AIEngines

Authors: S. Achaq(1), V. Pouget(2), L. Artola(3), A. Urena(3), J. Boch(4)
1. Sorbonne université, France,
2. IES-CNRS, France,
3. ONERA, France,
4. Univ Montpellier, France

Presenting author: Salma Achaq

We present the SEE laser testing methodology and associated results for a custom CNN hardware accelerator implemented in the AIEngines of the Versal SoC. Data events and application hangs are quantified. The optimized observability of the developed test-bench reveal details about data events propagation in the CNN layers, as well as artefacts to be considered also for particle beam testing.

PE-8

Comprehensive Analysis of Heavy-Ion Test Results on 112 Gbps High-Speed Serial Link IP

Authors: M. Glorieux(1), T. Lange(1), R. Gaillard(1), I. Nofal(1), D. Levacq(2), B. Said(3), R. Jain(4), M. Lerchenmueller(5)
1. IROC Technologies, France,
2. European Space Agency, ESTEC, Netherlands,
3. ESA, Netherlands,
4. Cadence Design Systems, Inc, USA,
5. Cadence Design Systems GmbH, Germany

Presenting author: Maximiien Glorieux

A 112Gbps High-Speed Serial-Link IP was tested under heavy ion irradiation, and different failure modes were identified and characterized in terms of cross-section and criticality at system level.

PE-9

Capabilities and Limitations of Pulsed Laser Testing for SEE Evaluation of a Deep Submicron Digital SoC

Authors: C. Elash(1), Z. Li(1), J. Xing(1), X. Lu(1), R. Basak(1), G. Belev(1), J. Wright(2), L. Chen(1)
1. University of Saskatchewan, Canada,
2. University of Wollongong, Australia

Presenting author: Christopher Elash

This work examines how pulsed laser testing reproduces single-event effects in a 22-nm radiation-hardened RISC-V SoC against heavy-ion data. SRAM trends agree qualitatively, while scan-order bias and logic-region response highlight limitations in system-level SEE evaluation.